An analog-to-digital converter (ADC) is one of core components of current applied electronic apparatus and communication apparatus. Due to the electronic market demand for portable electronic communication apparatus in recent years, low-power consumption and high-precision ADC has become the main development trend of ADC technology. As one of the main components of the ADC structure, a comparator, especially a high-speed and low-power consumption comparator, is very popular on the market.
FIGS. 1-2 illustrate schematic diagrams of representative comparators. The comparator illustrated in FIG. 1 is a comparator based on a structure of a latch 1 having a pre-static amplifier 2. The pre-static amplifier 2 enables the comparator to provide a small-signal gain. The comparator can withstand Kickback noise coupled to the input terminal due to a large jump in the output terminal of the latch 1, and have a fast speed. However, the comparator has an issue of large-static-power consumption.
FIG. 2 illustrates a comparator having a dynamic preamp amplifier 3 and a latch 4. The comparator is used to solve the large-power consumption issue. The input signal is amplified by using synchronous discharge time of node capacitors, to realize pre-amplification. The comparator illustrated in FIG. 2 not only overcomes the large-power consumption issue in the comparator illustrated in FIG. 1, and but also has a small Kickback noise.
However, conventional comparators have the issues of low speed and low gain. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.